Integrated electronic devices often have multiple cores, such as low voltage (LV) digital cores and high voltage (HV) analog cores. In many cases, each core may be capable of operating in different power modes. For example, during normal operation, a digital core may transition from a low-power mode (e.g., standby mode) to a high-power mode (e.g., active mode), where the current consumption increases.
As the inventors hereof have recognized, a low drop out (LDO) regulator providing the voltage supply to the digital core should have low quiescent current during standby mode, where the load current on the digital core is ultra low (e.g., ˜100 nA). However, such an LDO should also be able to provide the required load current (e.g., ˜5 mA) with a good transient response during the digital core's active mode.
To address these, and other concerns, systems and methods described herein provide techniques for adapting biasing conditions on an LDO to achieve a low quiescent current during the standby mode, and also to provide good transient response during the active mode.